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| www.motorola.com/semiconductors m68hc05 microcontrollers MC68HC05J1A/d rev. 3, 4/2002 MC68HC05J1A mc68hcl05j1a technical data mc68hsc05j1a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola 3 MC68HC05J1A mc68hcl05j1a mc68hsc05j1a technical data to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 4 motorola technical data revision history date revision level description page number(s) july, 2001 2.0 10.5 thermal characteristics ? in table under thermal resistance, device numbers corrected 97 section 12. ordering information ? added table 12-1. mc order numbers for clarity 111 april, 2002 3.0 update world wide web address 112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola list of sections 5 technical data ? MC68HC05J1A list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 17 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. central processor unit (cpu) . . . . . . . . . . . . 33 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 section 6. low-power modes. . . . . . . . . . . . . . . . . . . . . . 55 section 7. parallel input/output (i/o). . . . . . . . . . . . . . . . 61 section 8. multifunction timer. . . . . . . . . . . . . . . . . . . . . 71 section 9. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 77 section 10. electrical specifications . . . . . . . . . . . . . . . . 95 section 11. mechanical specifications . . . . . . . . . . . . . 109 section 12. ordering information . . . . . . . . . . . . . . . . . 111 appendix a. mc68hcl05j1a. . . . . . . . . . . . . . . . . . . . . 117 appendix b. mc68hsc05j1a . . . . . . . . . . . . . . . . . . . . 123 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 6 list of sections motorola list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola table of contents 7 technical data ? MC68HC05J1A table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.6.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.6.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.4 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.5 pa7 ? pa0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.6 pb5 ? pb0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.4 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .28 2.6 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 8 table of contents motorola table of contents section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2.1 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2.2 pa3 ? pa0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.3.2.3 irq status and control register . . . . . . . . . . . . . . . . . . .45 4.3.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.3.1 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.3.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.3 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.3.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.3.3 computer operating properly (cop) reset. . . . . . . . . . . . .51 5.3.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC05J1A ? rev. 3.0 technical data motorola table of contents 9 5.4 reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.2 i/o port registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.3 multifunction timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.4 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 6. low-power modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.5 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.6 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 section 7. parallel input/output (i/o) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.3 i/o port function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.4 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.4.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4.4 port a external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.5.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.5.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 10 table of contents motorola table of contents section 8. multifunction timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.3 timer status and control register . . . . . . . . . . . . . . . . . . . . . .73 8.4 cop watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 9. instruction set 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .82 9.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .83 9.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .86 9.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 section 10. electrical specifications 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC05J1A ? rev. 3.0 technical data motorola table of contents 11 10.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . . .97 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .99 10.8 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .100 10.9 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 10.10 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 section 11. mechanical specifications 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 11.3 20-pin plastic dual in-line package (pdip). . . . . . . . . . . . . .110 11.4 20-pin small outline integrated circuit package (soic) . . . .110 section 12. ordering information 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.4 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.5 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.6 diskettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.7 eproms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 12.8 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .114 12.9 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 12 table of contents motorola table of contents appendix a. mc68hcl05j1a a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 a.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 118 a.4 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 appendix b. mc68hsc05j1a b.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 b.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124 b.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 b.5 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola list of figures 13 technical data ? MC68HC05J1A list of figures figure title page 1-1 MC68HC05J1A block diagram . . . . . . . . . . . . . . . . . . . . . . 20 1-2 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1-3 bypassing layout recommendation . . . . . . . . . . . . . . . . . .22 1-4 crystal connections with feedback resistor mask option . . . . . . . . . . . . . . .23 1-5 crystal connections without feedback resistor mask option. . . . . . . . . . . . .23 1-6 ceramic resonator connections with feedback resistor mask option . . . . . . . . . . . . . . .24 1-7 ceramic resonator connections without feedback resistor mask option. . . . . . . . . . . . .24 1-8 rc oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1-9 external clock connections . . . . . . . . . . . . . . . . . . . . . . . . . 25 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3-3 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 38 4-1 external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4-2 irq status and control register (iscr) . . . . . . . . . . . . . . . 45 4-3 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 14 list of figures motorola list of figures figure title page 4-4 interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 5-1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5-2 cop register (copr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6-1 stop/wait/halt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7-1 port a data register (porta). . . . . . . . . . . . . . . . . . . . . . .62 7-2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . .63 7-3 pulldown register a (pdra) . . . . . . . . . . . . . . . . . . . . . . . .64 7-4 port a i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7-5 port b data register (portb). . . . . . . . . . . . . . . . . . . . . . .67 7-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . .68 7-7 pulldown register b (pdrb) . . . . . . . . . . . . . . . . . . . . . . . .69 7-8 port b i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 8-1 multifunction timer block diagram. . . . . . . . . . . . . . . . . . . .72 8-2 timer status and control register (tscr) . . . . . . . . . . . . .73 8-3 timer counter register (tcntr) . . . . . . . . . . . . . . . . . . . .75 8-4 cop register (copr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 10-1 typical v oh /i oh (v dd = 5.0 v) . . . . . . . . . . . . . . . . . . . . . .101 10-2 typical v oh /i oh (v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . .101 10-3 typical v ol /i ol (v dd = 5.0 v) . . . . . . . . . . . . . . . . . . . . . .102 10-4 typical v ol /i ol (v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . .102 10-5 typical operating i dd (25 c) . . . . . . . . . . . . . . . . . . . . . . .103 10-6 typical wait mode i dd (25 c) . . . . . . . . . . . . . . . . . . . . . . 103 10-7 typical internal operating frequency for various v dd at 25 c ? rc option only . . . . . . . . .104 10-8 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .107 10-9 stop mode recovery timing . . . . . . . . . . . . . . . . . . . . . . .107 10-10 power-on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .108 10-11 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 a-1 maximum run mode i dd versus frequency . . . . . . . . . . .120 a-2 maximum wait mode i dd versus frequency . . . . . . . . . . .121 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola list of tables 15 technical data ? MC68HC05J1A list of tables table title page 4-1 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . .47 7-1 port a pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7-2 port b pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 8-1 real-time interrupt rate selection . . . . . . . . . . . . . . . . . . . .74 9-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . .82 9-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . .83 9-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . .85 9-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . .86 9-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 a-1 low-power output voltage (v dd = 1.8 ? 2.4 vdc) . . . . . . . . .118 a-2 low-power output voltage (v dd = 2.5 ? 3.6 vdc) . . . . . . . . .118 a-3 low-power supply current. . . . . . . . . . . . . . . . . . . . . . . . . .119 a-4 low-power pulldown current . . . . . . . . . . . . . . . . . . . . . . . .120 a-5 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 b-1 high-speed supply current . . . . . . . . . . . . . . . . . . . . . . . . .124 b-2 high-speed control timing (v dd = 5.0 v 10%). . . . . . . . .125 b-3 high-speed control timing (v dd = 3.3 v 10%) . . . . . . . .125 b-4 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 16 list of tables motorola list of tables f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola general description 17 technical data ? MC68HC05J1A section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 mcu structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.6.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.2 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.2.1 crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6.2.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.6.2.3 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.2.4 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.4 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.5 pa7 ? pa0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6.6 pb5 ? pb0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 18 general description motorola general description 1.2 introduction the MC68HC05J1A is a member of the low-cost, high-performance m68hc05 family of 8-bit microcontroller units (mcu). the m68hc05 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the popular m68hc05 central processor unit (cpu) and are available with a variety of subsystems, memory sizes and types, and package types. on-chip memory of the MC68HC05J1A includes: 1240 bytes of user read-only memory (rom) 64 bytes of user random-access memory (ram) information on the mc68hcl05j1a, a low-power version of the MC68HC05J1A, is introduced in appendix a. mc68hcl05j1a . information on the mc68hsc05j1a, a high-speed version of the MC68HC05J1A, is introduced in appendix b. mc68hsc05j1a . 1.3 features features of the mcu include: popular m68hc05 cpu memory-mapped input/output (i/o) registers 1240 bytes of user rom including eight user vector locations 64 bytes of user ram 14 bidirectional i/o pins with these features: ? software programmable pulldown devices ? four i/o pins with 8-ma current sinking capability ? four i/o pins with maskable external interrupt capability hardware mask and flag for external interrupts fully static operation with no minimum clock speed on-chip oscillator with connections for a crystal or ceramic resonator or for a resistor-capacitor (rc) network f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mask options MC68HC05J1A ? rev. 3.0 technical data motorola general description 19 15-bit multifunction timer computer operating properly (cop) watchdog power-saving stop (or halt), wait, and data-retention modes illegal address reset internal steering diode between reset and v dd pins 8 8 unsigned multiply instruction 20-pin plastic dual in-line package (pdip) 20-pin small outline integrated circuit package (soic) 1.4 mask options available MC68HC05J1A mask options are: on-chip oscillator connections: crystal/ceramic resonator connections or resistor-capacitor (rc) network connections crystal/ceramic resonator feedback resistor: connected or not connected (available only with crystal/ceramic oscillator mask option) stop instruction: enabled or disabled (converted to wait instruction) external interrupt pins: edge-triggered or edge- and level-triggered port a and port b pulldown resistors: connected or not connected cop watchdog timer: enabled or disabled port a external interrupt capability: enabled or disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 20 general description motorola general description 1.5 mcu structure figure 1-1 shows the structure of the MC68HC05J1A mcu. figure 1-1. MC68HC05J1A block diagram data direction register b port b pb5 pb4 pb3 pb2 pb1 pb0 0 00 000 0011 cpu control arithmetic/logic unit accumulator index register stack pointer 0 00 program counter 00 m68hc05 mcu reset condition code register 111hi ncz data direction register a port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 * * * * ** ** ** ** * 8-ma sink capability ** external interrupt capability cop watchdog and internal oscillator divide by two multifunction timer illegal address detect power cpu clock internal clock irq v dd v ss osc1 osc2 user rom ? 1240 bytes user ram ? 64 bytes reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC05J1A ? rev. 3.0 technical data motorola general description 21 1.6 pin assignments figure 1-2 shows the MC68HC05J1A pin assignments. figure 1-2. pin assignments 1.6.1 v dd and v ss v dd and v ss are the power supply and ground pins. the mcu operates from a single 5-v power supply. very fast signal transitions occur on the mcu pins, placing high short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu. place bypass capacitors as close to the mcu as possible, as figure 1-3 shows. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 osc1 osc2 pb5 pb4 pb3 pb2 pb1 pb0 v dd v ss reset irq pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 22 general description motorola general description figure 1-3. bypassing layout recommendation 1.6.2 osc1 and osc2 the osc1 and osc2 pins are the control connections for the on-chip oscillator. depending on the mask option selected, the oscillator can be driven by any one of these: crystal ceramic resonator resistor-capacitor (rc) network external clock signal the frequency of the internal oscillator is f osc . the mcu divides the internal oscillator output by two to produce the internal clock with a frequency of f op . an internal feedback resistor between the osc1 and osc2 pins is available as a mask option. the feedback resistor mask option is available only when the crystal/ceramic resonator mask option is also selected. 1.6.2.1 crystal with the crystal/ceramic resonator mask option, a crystal connected to the osc1 and osc2 pins can drive the on-chip oscillator. figure 1-4 and figure 1-5 show a typical crystal oscillator circuit for an at-cut, parallel resonant crystal. follow the crystal supplier ? s recommendations, as the crystal parameters determine the external component values v dd v ss c1 c2 mcu c2 v dd v ss v+ + c1 0.1 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC05J1A ? rev. 3.0 technical data motorola general description 23 required to provide reliable startup and maximum stability. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the crystal and capacitors as close as possible to the pins. note: use an at-cut crystal and not an at-strip crystal. the mcu may overdrive an at-strip crystal. figure 1-4. crystal connections with feedback resistor mask option figure 1-5. crystal connections without feedback resistor mask option mcu v dd v ss c1 c2 osc1 osc2 xtal c4 c3 v ss osc1 osc2 xtal c3 27 pf c4 27 pf mcu v dd v ss c1 c2 osc1 osc2 r xtal c4 c3 v ss osc1 osc2 10 m ? xtal c3 27 pf c4 27 pf r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 24 general description motorola general description 1.6.2.2 ceramic resonator to reduce cost, use a ceramic resonator in place of the crystal. use the circuit in figure 1-6 or figure 1-7 for a ceramic resonator and follow the resonator manufacturer ? s recommendations. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the resonator as close as possible to the pins. figure 1-6. ceramic resonator connections with feedback resistor mask option figure 1-7. ceramic resonator connections without feedback resistor mask option mcu v dd v ss c1 c2 osc1 osc2 ceramic c4 c3 osc1 osc2 ceramic c3 27 pf c4 27 pf resonator v ss resonator mcu v dd v ss c1 c2 osc1 osc2 r ceramic c4 c3 osc1 osc2 r 10 m ? ceramic c3 27 pf c4 27 pf resonator v ss resonator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments MC68HC05J1A ? rev. 3.0 technical data motorola general description 25 1.6.2.3 rc oscillator for maximum cost reduction, the rc oscillator mask option allows the configuration shown in figure 1-8 to drive the on-chip oscillator. the osc2 signal is a square wave, and the signal on osc1 is a triangular wave. the optimum frequency for the rc oscillator configuration is 2 mhz. mount the rc components as close as possible to the pins for startup stabilization and to minimize output distortion. figure 1-8. rc oscillator connections 1.6.2.4 external clock with the rc oscillator mask option, an external clock from another cmos-compatible device can drive the osc1 input. leave the osc2 pin unconnected, as figure 1-9 shows. figure 1-9. external clock connections mcu v dd v ss c1 c2 osc1 osc2 r osc1 osc2 r mcu osc1 osc2 external cmos clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 26 general description motorola general description 1.6.3 reset a logic 0 on the reset pin forces the mcu to a known startup state. see 5.3.2 external reset for more information. 1.6.4 irq the irq pin is an asynchronous external interrupt pin. see 4.3.2.1 irq pin . 1.6.5 pa7 ? pa0 pa7 ? pa0 are the pins of port a, a general-purpose, bidirectional i/o port. see 7.4 port a . 1.6.6 pb5 ? pb0 pb5 ? pb0 are the pins of port b, a general-purpose, bidirectional i/o port. see 7.5 port b . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola memory 27 technical data ? MC68HC05J1A section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.4 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . .28 2.6 read-only memory (rom). . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.2 introduction this section describes the organization of the on-chip memory. 2.3 memory map the central processor unit (cpu) can address 2 kbytes of memory space as shown in figure 2-1 . the read-only memory (rom) portion of memory holds the program instructions, fixed data, user-defined vectors, and interrupt service routines. the random-access memory (ram) portion of memory holds variable data. input/output (i/o) registers are memory-mapped so that the cpu can access their locations in the same way that it accesses all other memory locations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 28 memory motorola memory 2.4 input/output (i/o) section the first 32 addresses of the memory space, $0001 ? $001f, are the i/o section. these are the addresses of the i/o control registers, status registers, and data registers. see figure 2-2 . one i/o register shown in figure 2-2 is located outside the 32-byte i/o section: the computer operating properly (cop) register is mapped at $07f0. 2.5 random-access memory (ram) the 64 addresses from $00c0 to $00ff serve as both the user ram and the stack ram. the cpu uses five stack ram bytes to save all cpu register contents before processing an interrupt. during a subroutine call, the cpu uses two bytes to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 read-only memory (rom) the rom is located in two areas of the memory map: 1. addresses $0300 ? $07cf contain 1232 bytes of user rom. 2. addresses $07f8 ? $07ff contain 16 bytes of rom reserved for user vectors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory read-only memory (rom) MC68HC05J1A ? rev. 3.0 technical data motorola memory 29 figure 2-1. memory map port a data register port b data register unused unused port a data direction register port b data direction register unused unused timer status and control register timer counter register irq status and control register unused unused unused ? unused unused port a pulldown register port b pulldown register unused unused unused reserved cop register reserved reserved reserved reserved reserved reserved reserved timer vector (high byte) timer vector (low byte) external interrupt vector (high byte) external interrupt vector (low byte) software interrupt vector (high byte) software interrupt vector (low byte) reset vector (low byte) reset vector (low byte) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $001f * $07f0 $07f1 $07f2 $07f3 $07f4 $07f5 $07f6 $07f7 $07f8 $07f9 $07fb $07fa $07fc $07fd $07fe $07ff i/o registers 32 bytes $0000 $001f unused 160 bytes $0020 $00bf $00c0 user ram 64 bytes stack ram 64 bytes $00ff $0100 unused 512 bytes $02ff $0300 user vectors (rom) test rom 32 bytes user rom 1232 bytes $07cf $07d0 $07ef $07f0 $07ff * writing to bit 0 of $07f0 clears the cop watchdog. reading $07f0 returns rom data. 8 bytes reserved for test (rom) 8 bytes $07f7 $07f8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 30 memory motorola memory addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) see page 62. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 67. read: 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 unimplemented $0003 unimplemented $0004 data direction register a (ddra) see page 63. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 68. read: 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 unimplemented $0007 unimplemented $0008 timer status and control register (tscr) see page 73. read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset: 0 0 0 0 0 0 1 1 $0009 timer counter register (tcntr) see page 75. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $000a irq status and control register (iscr) see page 45. read: irqe irqf 00 0 0 0 write: irqr reset: 1 0 0 0 0 0 0 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o register summary (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory read-only memory (rom) MC68HC05J1A ? rev. 3.0 technical data motorola memory 31 $000b unimplemented $000f unimplemented $0010 pulldown register a (pdra) see page 64. read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset: 0 0 0 0 0 0 0 0 $0011 pulldown register b (pdrb) see page 69. read: write: pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 reset: u u 0 0 0 0 0 0 $0012 unimplemented $001e unimplemented $001f reserved read: rr r r r r rr write: reset: unaffected by reset $07f0 cop register (copr) see page 51. read: write: copc reset: u u u u u u u 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o register summary (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 32 memory motorola memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola central processor unit (cpu) 33 technical data ? MC68HC05J1A section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 introduction this section describes the central processor unit (cpu) registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 34 central processor unit (cpu) motorola central processor unit (cpu) 3.3 cpu registers figure 3-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 3-1. programming model accumulator (a) index 11 00 00 0 00 0 00 00 0 zc in 1h 11 0 4 75 condition code program stack half-carry flag interrupt mask negative flag zero flag carry/borrow flag 6 321 0 4 75 6 321 0 4 75 6 321 0 4 75 6 321 0 4 75 6 321 8 12 15 13 14 11 10 9 8 12 15 13 14 11 10 9 register (ccr) counter (pc) pointer (sp) register (x) sp pch pcl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC05J1A ? rev. 3.0 technical data motorola central processor unit (cpu) 35 3.3.1 accumulator the accumulator (a) shown in figure 3-2 is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. figure 3-2. accumulator (a) 3.3.2 index register in the indexed addressing modes, the cpu uses the byte in the index register (x) shown in figure 3-3 to determine the conditional address of the operand. see 9.3.5 indexed, no offset , 9.3.6 indexed, 8-bit offset , and 9.3.7 indexed, 16-bit offset for more information on indexed addressing. the 8-bit index register also can serve as a temporary data storage location. figure 3-3. index register (x) bit 7654321bit 0 read: write: reset: unaffected by reset bit 7654321bit 0 read: write: reset: unaffected by reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 36 central processor unit (cpu) motorola central processor unit (cpu) 3.3.3 stack pointer the stack pointer (sp) shown in figure 3-4 is a 16-bit register that contains the address of the next free location on the stack. during a reset or after the reset stack pointer (rsp) instruction, the stack pointer initializes to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. the 10 most significant bits of the stack pointer are fixed permanently at 0000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations. an interrupt uses five locations. figure 3-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: 0000000011000000 write: reset:0000000011111111 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers MC68HC05J1A ? rev. 3.0 technical data motorola central processor unit (cpu) 37 3.3.4 program counter the program counter (pc) shown in figure 3-5 is a 16-bit register that contains the address of the next instruction or operand to be fetched. the five most significant bits of the program counter are ignored internally and appear as 00000. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. figure 3-5. program counter (pc) bit 151413121110987654321 bit 0 read: 00000 write: reset:00000 loaded with vector from $07fe and $07ff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 38 central processor unit (cpu) motorola central processor unit (cpu) 3.3.5 condition code register the condition code register (ccr) shown in figure 3-6 is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of prior instructions. h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add without carry (add) or add with carry (adc) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. reset has no effect on the half-carry flag. i ? interrupt mask flag setting the interrupt mask (i) disables interrupts. if an interrupt request occurs while the interrupt mask is a logic 0, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after a reset, the interrupt mask is set and can be cleared only by a clear interrupt mask bit (cli), stop, or wait instruction. bit 7654321bit 0 read: 1 1 1 hinzc write: reset:1 1 1u1uuu = unimplemented u = unaffected figure 3-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) arithmetic/logic unit (alu) MC68HC05J1A ? rev. 3.0 technical data motorola central processor unit (cpu) 39 n ? negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result (bit 7 in the results is a logic 1). reset has no effect on the negative flag. z ? zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. reset has no effect on the zero flag. c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit. reset has no effect on the carry/borrow flag. 3.4 arithmetic/logic unit (alu) the arithmetic/logic unit (alu) performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction requires 11 internal clock cycles to complete this chain of operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 40 central processor unit (cpu) motorola central processor unit (cpu) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola interrupts 41 technical data ? MC68HC05J1A section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2.1 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.3.2.2 pa3 ? pa0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.3.2.3 irq status and control register . . . . . . . . . . . . . . . . . . .45 4.3.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.3.1 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.3.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.2 introduction this section describes how interrupts temporarily change the normal processing sequence. 4.3 interrupt sources these sources can generate interrupt requests: swi (software interrupt) instruction irq pin pa3 ? pa0 pins (mask option) multifunction timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 42 interrupts motorola interrupts an interrupt temporarily stops normal program execution to process a particular event. an interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. interrupt processing automatically saves the central processor unit (cpu) registers on the stack and loads the program counter with a user-defined vector address. 4.3.1 software interrupt the software interrupt (swi) instruction causes a non-maskable interrupt. 4.3.2 external interrupts these sources can generate external interrupts: irq pin pa3 ? pa0 pins (mask option) setting the i bit in the condition code register or clearing the irqe bit in the interrupt status and control register disables external interrupts. 4.3.2.1 irq pin an interrupt signal on the irq pin latches an external interrupt request. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the interrupt status and control register. if the i bit is clear and the irqe bit is set, the cpu then begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 4-1 shows the external interrupt logic. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt sources MC68HC05J1A ? rev. 3.0 technical data motorola interrupts 43 figure 4-1. external interrupt logic external interrupt triggering sensitivity is a mask option. the irq pin can be negative edge-triggered only or negative edge- and low level-triggered. with the mask option for an edge- and level-sensitive external interrupt trigger, a falling edge or a low level on the irq pin latches an external interrupt request. edge- and level-sensitive triggering allows the use of multiple wired-or external interrupt sources. an external interrupt request is latched as long as any source is holding the irq pin low. with the mask option for an edge-sensitive only external interrupt trigger, a falling edge on the irq pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level on the irq pin returns to logic 1 and then falls again to logic 0. level-sensitive trigger pa3 pa2 pa1 irq pa0 irq latch v dd (mask option) rst irq vector fetch irq status and control register external interrupt request irqe irqf irqr port a external interrupts enabled (mask option) internal data bus to bih & bil instruction processing r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 44 interrupts motorola interrupts 4.3.2.2 pa3?pa0 pins the mask option for port a external interrupts enables pins pa3 ? pa0 to serve as additional external interrupt sources. an interrupt signal on a pa3 ? pa0 pin latches an external interrupt request. after completing the current instruction, the cpu tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register and the irqe bit in the interrupt status and control register. if the i bit is clear and the irqe bit is set, the cpu then begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. external interrupt triggering sensitivity is a mask option. the pa3 ? pa0 pins can be positive edge-triggered only or positive edge- and high level-triggered. with the mask option for an edge- and level-sensitive external interrupt trigger, a rising edge or a high level on a pa3 ? pa0 pin latches an external interrupt request. edge- and level-sensitive triggering allows the use of multiple wired-or external interrupt sources. as long as any source is holding a pa3 ? pa0 pin high, an external interrupt request is latched, and the cpu continues to execute the interrupt service routine. with the mask option for an edge-sensitive only external interrupt trigger, a rising edge on a pa3 ? pa0 pin latches an external interrupt request. a subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logic 0 and then rises again to logic 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt sources MC68HC05J1A ? rev. 3.0 technical data motorola interrupts 45 4.3.2.3 irq status and control register the irq status and control register (iscr), shown in figure 4-2 , contains an external interrupt mask, an external interrupt flag, and a flag reset bit. irqe ? external interrupt request enable bit this read/write bit enables external interrupts. resets set the irqe bit. 1 = external interrupt processing enabled 0 = external interrupt processing disabled irqf ? external interrupt request flag the irq flag is a clearable, read-only bit that is set when an external interrupt request is pending. resets clear the irqf bit. 1 = interrupt request pending 0 = no interrupt request pending these conditions set the irq flag: a. an external interrupt signal on the irq pin b. an external interrupt signal on pin pa3, pa2, pa1, or pa0 when pa3 ? pa0 are enabled to serve as external interrupt sources the cpu clears the irq flag when fetching the interrupt vector. writing to the irq flag has no effect. clear the irq flag by writing a logic 1 to the irqr bit. irqr ? interrupt request reset bit this write-only bit clears the irq flag. 1 = irqf bit cleared 0 = no effect address: $000a bit 7654321bit 0 read: irqe irqf 0000 0 write: irqr reset:10000000 = unimplemented figure 4-2. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 46 interrupts motorola interrupts 4.3.3 timer interrupts the multifunction timer can generate these interrupts: timer overflow interrupt real-time interrupt setting the i bit in the condition code register disables timer interrupts. 4.3.3.1 timer overflow interrupt a timer overflow interrupt request occurs if the timer overflow flag, tof, becomes set while the timer overflow interrupt enable bit, toie, is also set. see 8.3 timer status and control register . 4.3.3.2 real-time interrupt a real-time interrupt request occurs if the real-time interrupt flag, rtif, becomes set while the real-time interrupt enable bit, rtie, is also set. see 8.3 timer status and control register . 4.4 interrupt processing the cpu takes these actions to begin servicing an interrupt: stores the cpu registers on the stack in the order shown in figure 4-3 sets the i bit in the condition code register to prevent further interrupts loads the program counter with the contents of the appropriate interrupt vector locations: ? $07fc and $07fd (software interrupt vector) ? $07fa and $07fb (external interrupt vector) ? $07f8 and $07f9 (timer interrupt vector) the return-from-interrupt (rti) instruction causes the cpu to recover the cpu registers from the stack as shown in figure 4-3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt processing MC68HC05J1A ? rev. 3.0 technical data motorola interrupts 47 figure 4-3. stacking order table 4-1 summarizes the reset and interrupt sources and vector assignments. table 4-1. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on reset pin cop watchdog (1) illegal address 1. the cop watchdog is a mask option. none none none none none 1 1 1 1 $07fe ? $07ff software interrupt (swi) user code none none same priority as instruction $07fc ? $07fd external interrupt irq pin pa3 pin (2) pa2 pin (2) pa1 pin (2) pa0 pin (2) 2. port a external interrupt capability is a mask option. irqe bit i bit 2 $07fa ? $07fb timer interrupts tof bit rtif bit tofe bit rtie bit i bit 3 $07f8 ? $07f9 condition code register $00c0 (bottom of stack) $00c1 $00c2 accumulator index register program counter (high byte) program counter (low byte) $00fd $00fe $00ff (top of stack) 1 2 3 4 5 5 4 3 2 1 unstacking order stacking order f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 48 interrupts motorola interrupts figure 4-4 shows the sequence of events caused by an interrupt. figure 4-4. interrupt flowchart external interrupt? i bit set? from reset timer interrupt? fetch next instruction swi instruction? rti instruction? stack pcl, pch, x, a, ccr set i bit load pc with interrupt vector yes yes yes yes yes unstack ccr, a, x, pch, pcl execute instruction clear irq latch no no no no no f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola resets 49 technical data ? MC68HC05J1A section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.3 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.3.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.3.3 computer operating properly (cop) reset. . . . . . . . . . . . .51 5.3.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4 reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.1 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.2 i/o port registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 5.4.3 multifunction timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.4 cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 introduction this section describes the four reset sources and how they initialize the microcontroller unit (mcu). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 50 resets motorola resets 5.3 reset types a reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. these conditions produce a reset: initial power-up (power-on reset) a logic 0 applied to the reset pin (external reset) timeout of the mask-optional computer operating properly (cop) watchdog (cop reset) an opcode fetch from an address not in the memory map (illegal address reset) figure 5-1 is a block diagram of the reset sources. figure 5-1. reset sources 5.3.1 power-on reset a positive transition on the v dd pin generates a power-on reset. the power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. v dd reset reset latch internal address bus r cop watchdog (mask option) power-on reset illegal address reset rst to cpu internal clock and subsystems f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets reset types MC68HC05J1A ? rev. 3.0 technical data motorola resets 51 a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if the reset pin is at logic 0 at the end of 4064 t cyc , the mcu remains in the reset condition until the signal on the reset pin goes to logic 1. 5.3.2 external reset a logic 0 applied to the reset pin for one and one-half t cyc generates an external reset. a schmitt trigger senses the logic level at the reset pin. 5.3.3 computer operating properly (cop) reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. see 8.4 cop watchdog . to clear the cop watchdog and prevent a cop reset, write a logic 0 to bit 0 (copc) of the cop register at location $07f0. the cop register, shown in figure 5-2 , is a write-only register that returns the contents of a rom location when read. the cop watchdog function is a mask option. copc ? cop clear bit copc is a write-only bit. periodically writing a logic 0 to copc prevents the cop watchdog from resetting the mcu. address: $07f0 bit 7654321bit 0 read: write: copc reset:uuuuuuu0 = unimplemented u = unaffected by reset figure 5-2. cop register (copr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 52 resets motorola resets 5.3.4 illegal address reset an opcode fetch from an address that is not in the rom (locations $0300 ? $07ff) or the ram (locations $00c0 ? $00ff) generates an illegal address reset. 5.4 reset states this subsection describes how resets initialize the mcu. 5.4.1 cpu a reset has the following effects on the cpu: loads the stack pointer with $ff sets the i bit in the condition code register, inhibiting interrupts sets the irqe bit in the interrupt status and control register loads the program counter with the user-defined reset vector from locations $07fe and $07ff clears the stop latch, enabling the cpu clock clears the wait latch, waking the cpu from the wait mode 5.4.2 i/o port registers a reset has these effects on i/o port registers: clears bits ddra7 ? ddra0 in data direction register a so that port a pins are inputs clears bits pdia7 ? pdia0 in pulldown register a so that port a pulldown devices are enabled clears bits ddrb5 ? ddrb0 in data direction register b so that port b pins are inputs clears bits pdib5 ? pdib0 in pulldown register b so that port b pulldown devices are enabled has no effect on port a or port b data registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets reset states MC68HC05J1A ? rev. 3.0 technical data motorola resets 53 5.4.3 multifunction timer a reset has these effects on the multifunction timer: clears the timer status and control register clears the timer counter register 5.4.4 cop watchdog a reset clears the cop watchdog, if the cop watchdog is enabled by mask option. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 54 resets motorola resets f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola low-power modes 55 technical data ? MC68HC05J1A section 6. low-power modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.5 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.6 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.2 introduction this section describes the four low-power modes: stop mode wait mode halt mode (mask option) data-retention mode 6.3 stop mode the stop instruction puts the microcontroller unit (mcu) in its lowest power-consumption mode and has these effects on the mcu: clears tof and rtif, the timer interrupt flags in the timer status and control register, removing any pending timer interrupts clears toie and rtie, the timer interrupt enable bits in the timer status and control register, disabling further timer interrupts clears the multifunction timer counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 56 low-power modes motorola low-power modes sets the irqe bit in the irq status and control register to enable external interrupts clears the i bit in the condition code register, enabling interrupts stops the internal oscillator, turning off the central processor unit (cpu) clock and the timer clock, including the computer operating properly (cop) watchdog the stop instruction does not affect any other registers or any input/output (i/o) lines. these conditions bring the mcu out of stop mode: an external interrupt signal on the irq pin ? a high-to-low transition on the irq pin loads the program counter with the contents of locations $07fa and $07fb. an external interrupt signal on a port a external interrupt pin ? if the mask option for the port a external interrupt function is selected, a low-to-high transition on a pa3 ? pa0 pin loads the program counter with the contents of locations $07fa and $07fb. external reset ? a logic 0 on the reset pin resets the mcu and loads the program counter with the contents of locations $07fe and $07ff. when the mcu exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles. 6.4 wait mode the wait instruction puts the mcu in an intermediate power-consumption mode and has these effects on the mcu: clears the i bit in the condition code register, enabling interrupts sets the irqe bit in the irq status and control register, enabling external interrupts stops the central processor unit (cpu) clock, but allows the internal oscillator and timer clock to continue to run the wait instruction does not affect any other registers or any i/o lines. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes halt mode MC68HC05J1A ? rev. 3.0 technical data motorola low-power modes 57 these conditions restart the cpu clock and bring the mcu out of wait mode: an external interrupt signal on the irq pin ? a high-to-low transition on the irq pin loads the program counter with the contents of locations $07fa and $07fb. an external interrupt signal on a port a external interrupt pin ? if the mask option for the port a external interrupt function is selected, a low-to-high transition on a pa3 ? pa0 pin loads the program counter with the contents of locations $07fa and $07fb. a timer interrupt ? a timer overflow or a real-time interrupt request loads the program counter with the contents of locations $07f8 and $07f9. a cop watchdog reset ? a timeout of the mask-optional cop watchdog resets the mcu and loads the program counter with the contents of locations $07fe and $07ff. software can enable real-time interrupts so that the mcu can periodically exit wait mode to reset the cop watchdog. external reset ? a logic 0 on the reset pin resets the mcu and loads the program counter with the contents of locations $07fe and $07ff. 6.5 halt mode if the mask option to disable the stop instruction is selected, a stop instruction puts the mcu in halt mode. the halt mode is identical to the wait mode, except that a recovery delay of 1 ? 4064 internal clock cycles occurs when the mcu exits the halt mode. if the mask option to disable the stop instruction is selected, the cop watchdog cannot be inadvertently turned off by a stop instruction. figure 6-1 shows the sequence of events in stop, wait, and halt modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 58 low-power modes motorola low-power modes figure 6-1. stop/wait/halt flowchart stop stop disabled? clear i bit in ccr set irqe bit in iscr clear tof, rtif, toie, and rtie bits in tscr turn off internal oscillator external reset? external interrupt? no no no turn on internal oscillator start stabilization delay yes yes halt yes end of stabilization delay? yes no yes no no no cop reset? timer interrupt? external interrupt? external reset? clear i bit in ccr set irqe bit in iscr turn off cpu clock timer clock active yes yes yes wait yes no no no cop reset? timer interrupt? external interrupt? external reset? clear i bit in ccr set irqe bit in iscr turn off cpu clock timer clock active yes yes yes no no turn on cpu clock 1. load pc with reset vector or 2. service interrupt a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes data-retention mode MC68HC05J1A ? rev. 3.0 technical data motorola low-power modes 59 6.6 data-retention mode in data-retention mode, the mcu retains random-access memory (ram) contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in data-retention mode: 1. drive the reset pin to logic 0. 2. lower the v dd voltage. the reset pin must remain low continuously during data-retention mode. to take the mcu out of data-retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to logic 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 60 low-power modes motorola low-power modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola parallel input/output (i/o) 61 technical data ? MC68HC05J1A section 7. parallel input/output (i/o) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.3 i/o port function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.4 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.4.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.3 pulldown register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4.4 port a external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7.5.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.5.3 pulldown register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 7.2 introduction this section describes the two bidirectional input/output (i/o) ports. 7.3 i/o port function the 14 bidirectional i/o pins form two parallel i/o ports. each i/o pin is programmable as an input or an output. the contents of the data direction registers determine the data direction of each i/o pin. all 14 i/o pins have mask-optional, software-programmable pulldown devices. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 62 parallel input/output (i/o) motorola parallel input/output (i/o) 7.4 port a port a is an 8-bit, general-purpose, bidirectional i/o port with these features: programmable pulldown devices (mask option) 8-ma current sinking capability (pins pa7 ? pa4) external interrupt capability (mask option: pins pa3 ? pa0) 7.4.1 port a data register the port a data register (porta) contains a bit for each of the port a pins. when a port a pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port a pin is programmed to be an input, reading the port a data register returns the logic state of the pin. pa7 ? pa0 ? port a data bits these read/write bits are software-programmable. data direction of each bit is under the control of the corresponding bit in data direction register a. resets have no effect on port a data. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 7-1. port a data register (porta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port a MC68HC05J1A ? rev. 3.0 technical data motorola parallel input/output (i/o) 63 7.4.2 data direction register a the contents of data direction register a (ddra) determine whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the associated port a pin; a logic 0 disables the output buffer. a reset initializes all ddra bits to 0, configuring all port a pins as inputs. ddra7 ? ddra0 ? port a data direction bits these read/write bits control port a data direction. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing ddra bits from logic 0 to logic 1. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 7-2. data direction register a (ddra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 64 parallel input/output (i/o) motorola parallel input/output (i/o) 7.4.3 pulldown register a all port a pins have mask-optional, programmable pulldown devices that typically sink 100 a. clearing the pdia7 ? pdia0 bits in pulldown register a (pdra) turns on the pulldown devices. see figure 7-3 . pulldown register a can turn on a port a pulldown device only when the port a pin is an input. reset clears the pdia7 ? pdia0 bits, turning on all the port a pulldown devices. pdia7 ? pdia0 ? port a pulldown inhibit bits writing logic 0s to these write-only bits turns on the port a pulldown devices. reading pulldown register a returns undefined data. 1 = corresponding port a pin pulldown device turned off 0 = corresponding port a pin pulldown device turned on note: avoid a floating port a input by clearing its pulldown register bit before changing its ddra bit from logic 1 to logic 0. do not use read-modify-write instructions on pulldown register a. address: $0010 bit 7654321bit 0 read: write: pdia7 pdia6 pdia5 pdia4 pdia3 pdia2 pdia1 pdia0 reset:00000000 = unimplemented figure 7-3. pulldown register a (pdra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port a MC68HC05J1A ? rev. 3.0 technical data motorola parallel input/output (i/o) 65 7.4.4 port a external interrupts if the port a external interrupt mask option is selected, the pa3 ? pa0 pins serve as external interrupt pins in addition to the irq pin. external interrupt triggering sensitivity is a mask option. the pa3 ? pa0 pins can be positive edge-triggered or positive edge- and high level-triggered. note: when testing for external interrupts, the bih and bil instructions test the voltage on the irq pin, not the state of the internal irq signal. therefore, bih and bil cannot test the port a external interrupt pins. figure 7-4 shows the port a i/o logic. figure 7-4. port a i/o circuit pax external interrupt request data direction register a bit ddrax port a data register bit pax pulldown register a bit pdiax read $0004 write $0004 write $0000 read $0000 write $0010 100- a pulldown device pulldown devices enabled (mask option) reset internal data bus 8-ma sink capability (pins pa7 ? pa4) (pins pa3 ? pa0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 66 parallel input/output (i/o) motorola parallel input/output (i/o) when a port a pin is programmed as an output, reading the port bit actually reads the value of the data latch and not the voltage on the pin itself. when a port a pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddr bit. table 7-1 summarizes the operations of the port a pins. table 7-1. port a pin functions pulldown mask option control bits i/o pin mode accesses to pdra accesses to ddra accesses to porta pdiax ddrax read write read/write read write no x (1) 0 input, hi-z u (2) pdia7 ? pdia0 ddra7 ? ddra0 pin pa7 ? pa0 no x 1 output u pdia7 ? pdia0 ddra7 ? ddra0 pa7 ? pa0 pa7 ? pa0 yes 0 0 input, pulldown on updia7 ? pdia0 ddra7 ? ddra0 pin pa7 ? pa0 yes 0 1 output, pulldown on updia7 ? pdia0 ddra7 ? ddra0 pa7 ? pa00 pa7 ? pa0 yes 1 0 input, hi-z updia7 ? pdia0 ddra7 ? ddra0 pin pa7 ? pa0 yes 1 1 output u pdia7 ? pdia0 ddra7 ? ddra0 pa7 ? pa0 pa7 ? pa0 1. x = don ? t care 2. u = undefined f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port b MC68HC05J1A ? rev. 3.0 technical data motorola parallel input/output (i/o) 67 7.5 port b port b is a 6-bit, general-purpose, bidirectional i/o port with programmable pulldown devices. 7.5.1 port b data register the port b data register (portb) contains a bit for each of the port b pins. when a port b pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port b pin is programmed to be an input, reading the port b data register returns the logic state of the pin. pb5 ? pb0 ? port b data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in the port b data direction register. bits 7 and 6 ? not used bits 7 and 6 always read as logic 0s. writes to these bits have no effect. address: $0001 bit 7654321bit 0 read: 0 0 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset = unimplemented figure 7-5. port b data register (portb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 68 parallel input/output (i/o) motorola parallel input/output (i/o) 7.5.2 data direction register b the contents of data direction register b (ddrb) determine whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the associated port b pin; a logic 0 disables the output buffer. a reset initializes all ddrb bits to logic 0, configuring all port b pins as inputs. ddrb5 ? ddrb0 ? data direction bits these read/write bits control port b data direction. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input bit 7 and 6 ? not used bits 7 and 6 always read as logic 0s. writes to these bits have no effect. note: avoid glitches on port b pins by writing to the port b data register before changing ddrb bits from logic 0 to logic 1. address: $0005 bit 7654321bit 0 read: 0 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 7-6. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port b MC68HC05J1A ? rev. 3.0 technical data motorola parallel input/output (i/o) 69 7.5.3 pulldown register b all port b pins have mask-optional, programmable pulldown devices that typically sink 100 a. clearing any of the pdib5 ? pdib0 bits in pulldown register b (pdrb) turns on the pulldown devices. see figure 7-7 . pulldown register b can turn on a port b pulldown device only when the port b pin is an input. reset clears bits pdib5 ? pdib0, turning on the port b pulldown devices. pdib5 ? pdib0 ? pulldown inhibit bits writing logic 0s to these write-only bits turns on the port b pulldown devices. reading pulldown register b returns undefined data. 1 = corresponding port b pin pulldown device turned off 0 = corresponding port b pin pulldown device turned on bits 7 and 6 ? not used note: avoid a floating port b input by clearing its pulldown register bit before changing its ddrb bit from logic 1 to logic 0. do not use read-modify-write instructions on pulldown register b. figure 7-8 shows the port b i/o logic. reading a port b output actually reads the value of the data latch and not the voltage on the pin itself. when a port b pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddr bit. table 7-2 summarizes the operation of the port b pins. address: $0011 bit 7654321bit 0 read: write: pdib5 pdib4 pdib3 pdib2 pdib1 pdib0 reset: 000000 = unimplemented figure 7-7. pulldown register b (pdrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 70 parallel input/output (i/o) motorola parallel input/output (i/o) figure 7-8. port b i/o circuit pbx data direction register b bit ddrbx port b data register bit pbx pulldown register b bit pdibx read $0005 write $0005 write $0001 read $0001 write $0011 100- a pulldown device pulldown devices enabled (mask option) reset internal data bus table 7-2. port b pin functions pulldown mask option control bits i/o pin mode accesses to pdrb accesses to ddrb accesses to portb pdibx ddrbx read write read/write read write no x (1) 0 input, hi-z u (2) pdib7 ? pdib0 ddrb7 ? ddrb0 pin pb7 ? pb0 no x 1 output u pdib7 ? pdib0 ddrb7 ? ddrb0 pb7 ? pb0 pb7 ? pb0 yes 0 0 input, pulldown on updib7 ? pdib0 ddrb7 ? ddrb0 pin pb7 ? pb0 yes 0 1 output, pulldown on updib7 ? pdib0 ddrb7 ? ddrb0 pb7 ? pb0 pb7 ? pb0 yes 1 0 input, hi-z updib7 ? pdib0 ddrb7 ? ddrb0 pin pb7 ? pb0 yes 1 1 o utp ut u pdib7 ? pdib0 ddrb7 ? ddrb0 pb7 ? pb0 pb7 ? pb0 1. x = don ? t care 2. u = undefined f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola multifunction timer 71 technical data ? MC68HC05J1A section 8. multifunction timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 8.3 timer status and control register . . . . . . . . . . . . . . . . . . . . . .73 8.4 cop watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 8.2 introduction this section describes the operation of the multifunction timer and the computer operating properly (cop) watchdog. figure 8-1 shows the organization of the timer subsystem. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 72 multifunction timer motorola multifunction timer figure 8-1. multifunction timer block diagram timer counter register ($0009) least significant 8 bits of 15-stage ripple counter overflow 4 internal clock (xtal 2) timer status/control register ($0008) tof rtif toie rtie tofr rtifr rt1 rt0 rti rate select 2 2 2 2 2 2 2 power-on reset (por) most significant 7 bits of 15-stage ripple counter 2 2 2 s r q interrupt request cop watchdog reset internal data bus internal data bus clear cop watchdog f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multifunction timer timer status and control register MC68HC05J1A ? rev. 3.0 technical data motorola multifunction timer 73 8.3 timer status and control register the read/write timer status and control register (tscr) contains these bits: timer interrupt enable bits timer interrupt flags timer interrupt flag reset bits timer interrupt rate select bits tof ? timer overflow flag this read-only flag becomes set when the first eight stages of the counter roll over from $ff to $00. tof generates a timer overflow interrupt request if toie is also set. clear tof by writing a logic 1 to the tofr bit. writing to tof has no effect. reset clears tof. rtif ? real-time interrupt flag this read-only flag becomes set when the selected real-time interrupt (rti) output becomes active. rtif generates a real-time interrupt request if rtie is also set. clear rtif by writing a logic 1 to the rtifr bit. writing to rtif has no effect. reset clears rtif. toie ? timer overflow interrupt enable bit this read/write bit enables timer overflow interrupts. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled address: $0008 bit 7654321bit 0 read: tof rtif toie rtie 00 rt1 rt0 write: tofr rtifr reset:00000011 = unimplemented figure 8-2. timer status and control register (tscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 74 multifunction timer motorola multifunction timer rtie ? real-time interrupt enable bit this read/write bit enables real-time interrupts. 1 = real-time interrupts enabled 0 = real-time interrupts disabled tofr ? timer overflow flag reset bit writing a logic 1 to this write-only bit clears the tof bit. tofr always reads as logic 0. reset clears tofr. rtifr ? real-time interrupt flag reset bit writing a logic 1 to this write-only bit clears the rtif bit. rtifr always reads as logic 0. reset clears rtifr. rt1 and rt0 ? real-time interrupt select bits 1 and 0 these read/write bits select one of four rti rates, as shown in table 8-1 . because the selected rti output drives the cop watchdog, changing the real-time interrupt rate also changes the counting rate of the cop watchdog. reset sets rt1 and rt0. note: changing rt1 and rt0 when a cop timeout is imminent or uncertain may cause a real-time interrupt request to be missed or an additional real-time interrupt request to be generated. clear the cop timer just before changing rt1 and rt0. table 8-1. real-time interrupt rate selection rt1:rt0 number of cycles to rti rti period (1) 1. at 2-mhz bus, 4-mhz xtal, 0.5 s per cycle number of cycles to cop reset cop timeout period (1) 0 0 2 14 = 16,384 8.2 ms 2 17 = 131,072 65.5 ms 0 1 2 15 = 32,768 16.4 ms 2 18 = 262,144 131.1 ms 1 0 2 16 = 65,536 32.8 ms 2 19 = 524,288 262.1 ms 1 1 2 17 = 131,072 65.5 ms 2 20 = 1,048,576 524.3 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multifunction timer timer status and control register MC68HC05J1A ? rev. 3.0 technical data motorola multifunction timer 75 a 15-stage ripple counter is the core of the timer. the value of the first eight stages is readable at any time from the read-only timer counter register (tcntr). power-on clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released, clearing the counter again and allowing the mcu to come out of reset. a timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. address: $0009 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 8-3. timer counter register (tcntr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 76 multifunction timer motorola multifunction timer 8.4 cop watchdog four counter stages at the end of the timer make up the mask-optional computer operating properly (cop) watchdog. (see figure 8-4 .) the cop watchdog is a software error detection system that automatically times out and resets the mcu if not cleared periodically by a program sequence. writing a logic 0 to bit 0 of the cop register clears the cop watchdog and prevents a cop reset. copc ? cop clear bit this write-only bit resets the cop watchdog. reading address $07f0 returns the rom data at that address. note: the stop instruction turns off the cop watchdog. in applications that depend on the cop watchdog, the stop instruction can be disabled by a mask option. address: $07f0 bit 7654321bit 0 read: write: copc reset:uuuuuuu0 = unimplemented figure 8-4. cop register (copr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 77 technical data ? MC68HC05J1A section 9. instruction set 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 9.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .82 9.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .83 9.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .84 9.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . .86 9.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 9.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 9.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 78 instruction set motorola instruction set 9.2 introduction the microcontroller unit (mcu) instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 9.3 addressing modes the central processor unit (cpu) uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set addressing modes MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 79 9.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 9.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 9.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 9.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 80 instruction set motorola instruction set 9.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 9.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000 ? $01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 9.3.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 81 9.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 9.4 instruction types the mcu instructions fall into five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 82 instruction set motorola instruction set 9.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 9-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 83 9.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 9-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one ? s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 84 instruction set motorola instruction set 9.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 85 table 9-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 86 instruction set motorola instruction set 9.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 9-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 87 9.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 9-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 88 instruction set motorola instruction set 9.5 instruction set summary table 9-6. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 89 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0inh98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 9-6. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 90 instruction set motorola instruction set clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 9-6. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 91 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0inh42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 9-6. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 92 instruction set motorola instruction set ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1inh99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ?? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x (a) ????? inh 97 2 table 9-6. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set opcode map MC68HC05J1A ? rev. 3.0 technical data motorola instruction set 93 9.6 opcode map see table 9-7 . tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ( ) negation (two ? s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 9-6. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 94 instruction set motorola instruction set table 9-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 tax 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 95 technical data ? MC68HC05J1A section 10. electrical specifications 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 10.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 10.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . . .97 10.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . . .99 10.8 3.3-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .100 10.9 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 10.10 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 10.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 96 electrical specifications motorola electrical specifications 10.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 10.7 5.0-volt dc electrical characteristics and 10.8 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ? 0.3 to +7.0 v input voltage v in v ss ? 0.3 to v dd +0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg ? 65 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications operating temperature range MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 97 10.4 operating temperature range 10.5 thermal characteristics rating symbol value unit operating temperature range MC68HC05J1Ap (1) , dw (2) MC68HC05J1Ac (3) p, cdw MC68HC05J1Av (4) p MC68HC05J1Avdw 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) 3. c = extended temperature range ( ? 40 c to +85 c) 4. v = automotive temperature range ( ? 40 c to +105 c) t a 0 to +70 ? 40 to +85 ? 40 to +105 ? 40 to +105 c characteristic symbol value unit maximum junction temperature t j 150 c thermal resistance MC68HC05J1Ap (1) MC68HC05J1Adw (2) 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) ja 68 85 c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 98 electrical specifications motorola electrical specifications 10.6 power considerations the average chip junction temperature, t j , in c can be obtained from: t j = t a + (p d x ja )(1) where: t a = ambient temperature in c ja = package thermal resistance, junction to ambient in c/w p d = p int + p i/o p int = i cc v cc = chip internal power dissipation p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o < p int and can be neglected. ignoring p i/o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: = p d x (t a + 273 c) + ja x (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . p d = t j + 273 c k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt dc electrical characteristics MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 99 10.7 5.0-volt dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%; v ss = 0 vdc; t a = ? 40 c to +85 c; values reflect average measurements at midpoint of voltage range at 25 c symbol min typ max unit output voltage i load = 10.0 a i load = ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage pa7 ? pa0, pb5 ? pb0 (i load = ? 0.8 ma) v oh v dd ? 0.8 ?? v output low voltage pa3 ? pa0, pb5 ? pb0 (i load = 1.6 ma) pa7 ? pa4 (i load = 8.0 ma) v ol ? ? ? ? 0.4 0.4 v input high voltage pa7 ? pa0, pb5 ? pb0, irq , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa7 ? pa0, pb5 ? pb0, irq , reset , osc1 v il v ss ? 0.2 v dd v supply current run (2) wait (3) stop (4) 25 c ? 40 c to +85 c 2. run (operating) i dd measured using external square wave clock source (f osc = 4.2 mhz) with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. 3. wait i dd measured using external square wave clock source (f osc = 4.2 mhz) with all inputs 0.2 v from rail and only the timer active. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il = 0.2 v. v ih =v dd ? 0.2 v. osc2 capacitance linearly affects wait i dd . 4. stop i dd measured with osc1 = v ss . all ports configured as inputs. v il =0.2v. v ih =v dd ? 0.2 v. i dd ? ? ? ? 3.0 1.6 0.2 2.0 4.0 2.5 10 20 ma ma a a i/o ports hi-z leakage current pa7 ? pa0, pb5 ? pb0 (pulldown device off) i il ?? 10 a input pulldown current pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 50 100 200 a input current reset , irq , osc1 i in ?? 1 a capacitance pa7 ? pa0, pb5 ? pb0 (input or output) reset , irq , osc1, osc2 c out c in ? ? ? ? 12 8 pf oscillator internal resistor (crystal/ceramic resonator mask option) r osc 1.0 2.0 3.0 m ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 100 electrical specifications motorola electrical specifications 10.8 3.3-volt dc electrical characteristics characteristic (1) 1. v dd = 3.3 vdc 10%; v ss = 0 vdc; t a = ? 40 c to +85 c; values reflect average measurements at midpoint of voltage range at 25 c symbol min typ max unit output voltage i load 10.0 a i load ? 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage pa7 ? pa0, pb5 ? pb0 (i load = ? 0.2 ma) v oh v dd ? 0.3 ?? v output low voltage pa3 ? pa0 (i load = ? 0.4 ma) pa7 ? pa4 (i load = 5.0 ma) v ol ? ? ? ? 0.3 0.3 v input high voltage pa7 ? pa0, pb5 ? pb0, irq , reset , osc1 v ih 0.7 v dd ? v dd v input low voltage pa7 ? pa0, pb5 ? pb0, irq , reset , osc1 v il v ss ? 0.2 v dd v supply current run (2) wait (3) stop (4) 25 c ? 40 c to +85 c 2. run (operating) i dd measured using external square wave clock source (f osc = 2.0 mhz) with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. 3. wait i dd measured using external square wave clock source (f osc = 2.0 mhz) with all inputs 0.2 v from rail and only the timer active. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il = 0.2 v. v ih =v dd ? 0.2 v. osc2 capacitance linearly affects wait i dd . 4. stop i dd measured with osc1 = v ss . all ports configured as inputs. v il =0.2v. v ih =v dd ? 0.2 v. i dd ? ? ? ? 1.0 0.5 0.1 1 2.0 1.0 5 10 ma ma a a i/o ports hi-z leakage current pa7 ? pa0, pb5 ? pb0 (pulldown device off) i il ?? 10 a input pulldown current pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 20 40 100 a input current reset , irq , osc1 i in ?? 1 a capacitance pa7 ? pa0, pb5 ? pb0 (input or output) reset , irq , osc1, osc2 c out c in ? ? ? ? 12 8 pf oscillator internal resistor (crystal/ceramic resonator mask option) r osc 1.0 2.0 3.0 m ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt dc electrical characteristics MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 101 figure 10-1. typical v oh /i oh (v dd = 5.0 v) figure 10-2. typical v oh /i oh (v dd = 3.3 v) 5.00 4.90 4.80 4.70 4.60 4.50 4.40 4.30 4.20 0.00 ? 3.00 ? 4.00 ? 5.00 ? 1.00 ? 2.00 i oh (ma) v oh (v) 85 c 25 c ? 40 c 85 c 25 c ? 40 c 3.35 3.25 3.15 3.05 2.95 2.85 2.75 2.65 2.55 0.00 ? 3.00 ? 4.00 ? 5.00 ? 1.00 ? 2.00 i oh (ma) v oh (v) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 102 electrical specifications motorola electrical specifications figure 10-3. typical v ol /i ol (v dd = 5.0 v) figure 10-4. typical v ol /i ol (v dd = 3.3 v) 0 100 200 300 400 500 600 700 800 0.00 6.00 8.00 10.00 2.00 4.00 i ol (ma) v ol (v) 85 c 25 c ? 40 c 0 100 200 300 400 500 600 700 800 0.00 6.00 8.00 10.00 2.00 4.00 i ol (ma) v ol (v) 85 c 25 c ? 40 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt dc electrical characteristics MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 103 figure 10-5. typical operating i dd (25 5.5 v 4.5 v 3.6 v 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 0.00 1.50 2.00 2.50 0.50 1.00 bus frequency (mhz) i dd (ma) 2.4 v 3.00 3.50 4.00 i dd (ma) 5.5 v 4.5 v 3.6 v 0.000 0.00 bus frequency (mhz) 2.4 v 2.00 1.00 3.00 4.00 5.00 0.500 1.000 1.500 2.000 2.500 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 104 electrical specifications motorola electrical specifications figure 10-7. typical internal operating frequency for various v dd at 25 ? rc option only 0.01 0.1 1.0 10.0 10 100 frequency (mhz) 1000 5.5 v 2.4 v 1.8 v 4.5 v 3.0 v 3.6 v 5.0 v resistance (k ? ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt control timing MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 105 10.9 5.0-volt control timing characteristic (1) 1. v dd = 5.0 vdc 10%; v ss = 0 vdc; t a = t l to t h symbol min max unit oscillator frequency crystal/ceramic resonator mask option (2) rc oscillator mask option external clock mask option 2. use only at-cut crystals. f osc ? dc ? 4.2 4.2 4.2 mhz internal operating frequency (f osc 2) crystal oscillator ceramic resonator rc oscillator external clock f op ? ? dc ? 2.1 2.1 2.1 2.1 mhz cycle time (1 f op )t cyc 476 ? ns reset pulse width low (edge-triggered) t rl 1.5 ? t cyc timer resolution (3) 3. the 2-bit timer prescaler is the limiting factor in determining timer resolution. t resl 4.0 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 125 ? ns irq interrupt pulse period t ilil (4) 4. the minimum period, t ilil or t ihih , should not be less than the number of cycles required to execute the interrupt service routine plus 19 t cyc . ? t cyc pa3 ? pa0 interrupt pulse width high (edge-triggered) t ihil 125 ? ns pa3 ? pa0 interrupt pulse period t ihih (4) ? t cyc osc1 pulse width t oh , t ol 200 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 106 electrical specifications motorola electrical specifications 10.10 3.3-volt control timing characteristic (1) 1. v dd = 3.3 vdc 10%; v ss = 0 vdc; t a = t l to t h symbol min max unit oscillator frequency crystal/ceramic resonator mask option (2) rc oscillator mask option external clock mask option 2. use only at-cut crystals. f osc ? dc ? 2.0 2.0 2.0 mhz internal operating frequency (f osc 2) crystal oscillator ceramic resonator rc oscillator external clock f op ? ? dc ? 1.0 1.0 1.0 1.0 mhz cycle time (1 f op )t cyc 1000 ? ns reset pulse width low (edge-triggered) t rl 1.5 ? t cyc timer resolution (3) 3. the 2-bit timer prescaler is the limiting factor in determining timer resolution. t resl 4.0 ? t cyc irq interrupt pulse width low (edge-triggered) t ilih 250 ? ns irq interrupt pulse period t ilil (4) 4. the minimum period, t ilil or t ihih , should not be less than the number of cycles required to execute the interrupt service routine plus 19 t cyc . ? t cyc pa3 ? pa0 interrupt pulse width high (edge-triggered) t ihil 250 ? ns pa3 ? pa0 interrupt pulse period t ihih (4) ? t cyc osc1 pulse width t oh , t ol 400 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt control timing MC68HC05J1A ? rev. 3.0 technical data motorola electrical specifications 107 figure 10-8. external interrupt timing figure 10-9. stop mode recovery timing irq (internal) t ilih t ilil t ilih irq pin irq 1 irq n . . . t ilih 4064 t cyc osc (note 1) t rl reset irq (note 2) irq (note 3) internal clock internal address bus notes: 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (note 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 108 electrical specifications motorola electrical specifications figure 10-10. power-on reset timing figure 10-11. external reset timing 1ffe 4064 t cyc v dd osc1 pin internal clock internal address bus notes: internal data bus 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (note 1) 1. power-on reset threshold is typically between 1 v and 2 v. 2. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl internal clock internal address bus notes: internal data bus 1ffe 1ffe 1ffe 1ffe 1fff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola mechanical specifications 109 technical data ? MC68HC05J1A section 11. mechanical specifications 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 11.3 20-pin plastic dual in-line package (pdip). . . . . . . . . . . . . .110 11.4 20-pin small outline integrated circuit package (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.2 introduction package dimensions for the MC68HC05J1A are provided in this section. the packages are: 20-pin plastic dual in-line package (pdip) 20-pin small outline integrated circuit package (soic) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 110 mechanical specifications motorola mechanical specifications 11.3 20-pin plastic dual in-line package (pdip) 11.4 20-pin small outline integrated circuit package (soic) ! -a- c k n e gf d 20 pl j 20 pl l m -t- 110 11 20 "# "# b case 738-03 f j dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) -a- -b- p 8x g 14x d 16x seating plane -t- s a m 0.010 (0.25) b s t 16 9 8 1 r x 45 m c k case 751 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola ordering information 111 technical data ? MC68HC05J1A section 12. ordering information 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 12.4 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.5 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .112 12.6 diskettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.7 eproms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 12.8 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . .114 12.9 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 115 12.2 introduction this section contains instructions for ordering custom-masked read-only memory (rom) microcontroller units (mcu). 12.3 mc order numbers table 12-1. mc order numbers package type temperature range order number 20-pin dual in-line package 0 c to 70 c MC68HC05J1Ap ? 40 c to 85 c MC68HC05J1Acp ? 40 c to 105 c MC68HC05J1Avp 20-pin small outline integrated circuit (soic) 0 c to 70 c MC68HC05J1Adw ? 40 c to 85 c MC68HC05J1Acdw ? 40 c to 105 c MC68HC05J1Avdw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 112 ordering information motorola ordering information 12.4 mcu ordering forms to initiate an order for a rom-based mcu, first obtain the current ordering form for the mcu from a motorola representative. submit these items when ordering mcus: a current mcu ordering form that is completely filled out (contact your motorola sales office for assistance.) a copy of the customer specification if the customer specification deviates from the motorola specification for the mcu customer ? s application program on one of the media listed in 12.5 application program media the current mcu ordering form is also available through the world wide web at http://www.motorola.com/semiconductors/ 12.5 application program media deliver the application program to motorola in one of these media: macintosh ? 1 3 1/2-inch diskette (double-sided double-density 800 kbytes or double-sided high-density 1.4 mbytes) ms-dos ? 2 or pc-dos ? 3 3 1/2-inch diskette (double-sided double-density 720 kbytes or double-sided high-density 1.44 mbytes) ms-dos ? or pc-dos ? 5 1/4-inch diskette (double-sided double-density 360 kbytes or double-sided high-density 1.2 mbytes) erasable, programmable read-only memory(s) (eprom) 2716, 2732, 2764, 27128, 27256, or 27512 (depending on the size of the memory map of the mcu) use positive logic for data and addresses. 1. macintosh is a registered trademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft, inc. 3. pc-dos is a registered trademark of international business machines corporation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information diskettes MC68HC05J1A ? rev. 3.0 technical data motorola ordering information 113 12.6 diskettes if submitting the application program on a diskette, clearly label the diskette with this information: customer name customer part number project or product name filename of object code date name of operating system that formatted diskette formatted capacity of diskette on diskettes, the application program must be in motorola ? s s-record format (s1 and s9 records), a character-based object file format generated by m6805 cross assemblers and linkers. note: begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom locations or leave all non-user rom locations blank. see the current mcu ordering form for additional requirements. if the memory map has two user rom areas with the same addresses, then write the two areas in separate files on the diskette. label the diskette with both filenames. in addition to the object code, a file containing the source code can be included. motorola keeps this code confidential and uses it only to expedite rom pattern generation in case of any difficulty with the object code. label the diskette with the filename of the source code. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 114 ordering information motorola ordering information 12.7 eproms if submitting the application program in an eprom, clearly label the eprom with this information: customer name customer part number checksum project or product name date note: begin the application program at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory map. write $00 in all non-user rom loctions. see the current mcu ordering form for additional requirements. submit the application program in one eprom large enough to contain the entire memory map. if the memory map has two user rom areas with the same addresses, then write the two areas on separate eproms. label the eproms with the addresses they contain. pack eproms securely in a conductive ic carrier for shipment. do not use styrofoam ? 1 . 12.8 rom program verification the primary use for the on-chip rom is to hold the customer ? s application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. motorola inputs the customer ? s application program code into a computer program that generates a listing verify file. the listing verify file represents the memory map of the mcu. the listing verify file contains the user rom code and may also contain non-user rom code, such as self-check code. motorola sends the customer a computer printout of the listing verify file along with a listing verify form. 1. styrofoam is a registered trademark of the dow chemical company. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information rom verification units (rvus) MC68HC05J1A ? rev. 3.0 technical data motorola ordering information 115 to aid the customer in checking the listing verify file, motorola will program the listing verify file into customer-supplied blank eproms or preformatted macintosh or dos disks. all original pattern media are filed for contractual purposes and are not returned. check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to motorola. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask. 12.9 rom verification units (rvus) after receiving the signed listing verify form, motorola manufactures a custom photographic mask. the mask contains the customer ? s application program and is used to process silicon wafers. the application program cannot be changed after the manufacture of the mask begins. motorola then produces ten mcus, called rvus, and sends the rvus to the customer. rvus are usually packaged in unmarked ceramic and tested to 5 vdc at room temperature. rvus are not tested to environmental extremes because their sole purpose is to demonstrate that the customer ? s user rom pattern was properly implemented. the ten rvus are free of charge with the minimum order quantity but are not production parts. rvus are not guaranteed by motorola quality assurance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 116 ordering information motorola ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola mc68hcl05j1a 117 technical data ? MC68HC05J1A appendix a. mc68hcl05j1a a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 a.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 118 a.4 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 a.2 introduction this appendix introduces the mc68hcl05j1a, a low-power version of the MC68HC05J1A. all of the information in this document applies to the mc68hcl05j1a with the exceptions given in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 118 mc68hcl05j1a motorola mc68hcl05j1a a.3 dc electrical characteristics the data in 10.7 5.0-volt dc electrical characteristics and 10.8 3.3-volt dc electrical characteristics applies to the mc68hcl05j1a with the exceptions shown in table a-1 , table a-2 , table a-3 , and table a-4 . table a-1. low-power output voltage (v dd = 1.8 ? 2.4 vdc) characteristic symbol min typ max unit output high voltage pa7 ? pa0, pb5 ? pb0 (i load = ? 0.1 ma) v oh v dd ? 0.3 ?? v output low voltage pa3 ? pa0 (i load = 0.2 ma) pa7 ? pa4 (i load = 2.0 ma) v ol ? ? ? ? 0.3 0.3 v table a-2. low-power output voltage (v dd = 2.5 ? 3.6 vdc) characteristic symbol min typ max unit output high voltage pa7 ? pa0, pb5 ? pb0 (i load = ? 0.2 ma) v oh v dd ? 0.3 ?? v output low voltage pa3 ? pa0 (i load = 0.4 ma) pa7 ? pa4 (i load = 5.0 ma) v ol ? ? ? ? 0.3 0.3 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hcl05j1a MC68HC05J1A ? rev. 3.0 technical data motorola mc68hcl05j1a 119 table a-3. low-power supply current characteristic symbol min typ (1) max unit supply current (v dd = 4.5 ? 5.5 vdc, f op = 2.1 mhz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) i dd ? ? ? ? 3.0 1.6 0.2 2.0 4.0 2.5 10 20 ma ma a a supply current (v dd = 2.5 ? 3.6 vdc, f op = 1.0 mhz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) i dd ? ? ? ? 1.0 0.5 0.1 1.0 2.0 1.0 5.0 10.0 ma ma a a supply current (v dd = 2.5 ? 3.6 vdc, f op = 500 khz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) i dd ? ? ? ? 0.5 250 0.1 1.0 1.0 500 5.0 10.0 ma a a a supply current (v dd = 1.8 ? 2.4 vdc, f op = 500 khz) run (2) wait (3) stop (4) 25 c 0 c to 70 c (standard) i dd ? ? ? ? 300 150 0.1 1.0 700 400 2 5 a a a a 1. typical values reflect average measurements at midpoint of voltage range at 25 c. 2. run (operating) i dd measured using external square wave clock source with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. 3. wait i dd measured using external square wave clock source with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il =0.2v, v ih =v dd ? 0.2 v. osc2 capacitance linearly affects wait i dd . 4. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v, v ih =v dd ? 0.2 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 120 mc68hcl05j1a motorola mc68hcl05j1a figure a-1. maximum run mode i dd versus frequency table a-4. low-power pulldown current characteristic symbol min typ (1) max unit pulldown current (v dd = 4.5 ? 5.5 vdc, f op = 2.1 mhz) pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 50 100 200 a pulldown current (v dd = 2.5 ? 3.6 vdc, f op = 1.0 mhz) pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 8 30 100 a pulldown current (v dd = 2.5 ? 3.6 vdc, f op = 500 khz) pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 31050 a pulldown current (v dd = 1.8 ? 2.4 vdc, f op = 500 khz) pa7 ? pa0, pb5 ? pb0 (pulldown device on) i il 31050 a 1. typical values reflect average measurements at midpoint of voltage range at 25 c. run i dd (ma) internal clock frequency (mhz) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.8 0.9 1.0 0.7 v dd = 2.5 v to 3.6 v v dd = 1.8 v to 2.4 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hcl05j1a MC68HC05J1A ? rev. 3.0 technical data motorola mc68hcl05j1a 121 figure a-2. maximum wait mode i dd versus frequency a.4 mc ordering information table a-5 gives order numbers for the available package types. wait i dd (ma) internal clock frequency (mhz) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.8 0.9 1.0 0.7 v dd = 2.5 v to 3.6 v v dd = 1.8 v to 2.4 v table a-5. mc order numbers package type temperature range order number 20-pin dual in-line package (dip) 0 c to 70 c mc68hcl05j1ap 20-pin small outline integrated circuit (soic) 0 c to 70 c mc68hcl05j1adw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 122 mc68hcl05j1a motorola mc68hcl05j1a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC05J1A ? rev. 3.0 technical data motorola mc68hsc05j1a 123 technical data ? MC68HC05J1A appendix b. mc68hsc05j1a b.1 contents b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 b.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124 b.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 b.5 mc ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 b.2 introduction this appendix introduces the mc68hsc05j1a, a high-speed version of the MC68HC05J1A. all of the information in this document applies to the mc68hsc05j1a with the exceptions given in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 124 mc68hsc05j1a motorola mc68hsc05j1a b.3 dc electrical characteristics the data in 10.7 5.0-volt dc electrical characteristics and 10.8 3.3-volt dc electrical characteristics applies to the mc68hsc05j1a with the exceptions given in table b-1 . table b-1. high-speed supply current characteristic symbol min typ (1) max unit supply current (v dd = 4.5 ? 5.5 vdc, f op = 4.0 mhz) run (2) wait (3) stop (4) 25 c ? 40 c to +85 c i dd ? ? ? ? 4.5 2.5 0.2 2.0 6.0 3.25 10 20 ma ma a a supply current (v dd = 3.0 ? 3.6 vdc, f op = 2.1 mhz run wait stop 25 c ? 40 c to +85 c i dd ? ? ? ? 2.0 1.0 0.1 1.0 4.0 2.0 5.0 10 ma ma a a 1. typical values reflect average measurements at midpoint of voltage range at 25 c. 2. run (operating) i dd measured using external square wave clock source with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. 3. wait i dd measured using external square wave clock source with all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. v il = 0.2 v, v ih =v dd ? 0.2 v. osc2 capacitance linearly affects wait i dd . 4. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v, v ih =v dd ? 0.2 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hsc05j1a MC68HC05J1A ? rev. 3.0 technical data motorola mc68hsc05j1a 125 b.4 control timing the data in 10.9 5.0-volt control timing and 10.10 3.3-volt control timing applies to the mc68hsc05j1a with the exceptions given in table b-2 and table b-3 . table b-2. high-speed control timing (v dd = 5.0 v oscillator frequency crystal oscillator (1) ceramic resonator external clock f osc ? ? ? 8.0 8.0 8.0 mhz internal operating frequency (f osc 2) crystal oscillator (1) ceramic resonator external clock f op ? ? ? 4.0 4.0 4.0 mhz cycle time (1 f op ) t cyc 250 ? ns irq pulse width low (edge-triggered) t ilil 63 ? ns pa3 ? pa0 interrupt pulse width (edge-triggered) t ihil 63 ? ns osc1 pulse width t oh or t ol 45 ? ns 1. use only at-cut crystals. table b-3. high-speed control timing (v dd = 3.3 v oscillator frequency crystal oscillator (1) ceramic resonator external clock f osc ? ? ? 4.2 4.2 4.2 mhz internal operating frequency (f osc 2) crystal oscillator (1) ceramic resonator external clock f op ? ? ? 2.1 2.1 2.1 mhz cycle time (1 f op ) t cyc 480 ns irq pulse width low (edge-triggered) t ilil 125 ? ns pa3 ? pa0 interrupt pulse width (edge-triggered) t ihil 125 ? ns osc1 pulse width t oh or t ol 90 ? ns 1. use only at-cut crystals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data MC68HC05J1A ? rev. 3.0 126 mc68hsc05j1a motorola mc68hsc05j1a b.5 mc ordering information table b-4 gives order numbers for the available package types. table b-4. mc order numbers package type temperature range order number 20-pin dual in-line package (dip) 0 c to 70 c mc68hsc05j1ap 20-pin small outline integrated circuit (soic) 0 c to 70 c mc68hsc05j1adw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 MC68HC05J1A/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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